1. Technical Field of the Invention
The invention relates to a method and a system for digitizing analog data. More particularly, the invention relates to a method and system for digitizing data that have been generated by an image sensor including a charge coupled device (CCD), a MOS-imager which is also known as a "charge injection device", and the like.
2. Description of Related Art
Charge coupled devices usually include a large number of light sensitive cells which generate and hold electric charges in response to light incident thereupon. The charges accumulated in each cell during a certain integration time are then transferred to one or more outputs of the CCD and are converted into electric voltages under the control of and in synchronism with a clock signal.
The analog data obtained in this way at the output of the CCD are supplied to an A/D-converter (ADC) via a conditioning circuit in which the offset and the gain factor are adapted to the input characteristics of the ADC.
A block diagram of a conventional CCD system of this type is illustrated in FIG. 3A. A CCD-array 10 supplies CCD-data V.sub.ccd to the conditioning circuit 12 the output of which is connected to the data input of ADC 14. In this example, the CCD-array is of a type which is controlled by a clock signal PHI, the inverted clock signal PHIn and a reset signal RS.
The waveforms of the signals V.sub.ccd, PHI and RS are shown in FIG. 3B. The signals PHI and PHIn serve as transport clock pulses by which the charges accumulated in the CCD cells are shifted through analog shift registers to the output port of the CCD-array which operates as a charge/voltage converter. The signal RS provides reset pulses for this charge/voltage converter. When the converter has been reset in the "low" period of the signal RS, the output port assumes a voltage V.sub.os which corresponds to a CCD cell which has not been exposed to light. At the subsequent transition of the signals PHI and PHIn, the next charge quantity is transferred to the output port and converted into a voltage V.sub.out which represents the amount of light that has been received by the corresponding CCD cell. This voltage V.sub.out has to be converted into digital data by the ADC 14. Accordingly, the ADC has to be controlled by an appropriate converter clock signal CONV in such a manner that the voltage of the signal V.sub.ccd is sampled and converted at a time t.sub.0 within the period in which this signal is valid, i.e. has the value V.sub.out.
As is shown in FIG. 3B, the converter clock signal CONV is a pulse signal which is obtained by delaying the clock signal PHI by a predetermined delay time T. The voltage values are digitized at the H/L-transitions of the signal CONV.
The converter clock signal CONV with the appropriate delay can be obtained in various ways, two of which are illustrated in FIGS. 4 and 5.
In FIG. 4, the signal CONV is derived from the clock signal PHI by means of a delay circuit 16. The delay circuit 16 may be formed for example by a series connection of a certain number of buffers each of which has a certain delay time, so that the total delay time is determined by the number of buffers. However, this implementation has the drawback that the delay times of commercially available buffers are known only within certain tolerances and the tolerances of the individual buffers in the series connection are accumulated, so that the total tolerance of the delay circuit 16 may become too large.
Alternatively, a delay circuit 16 may be used which is specifically designed for delaying a logic signal with a well defined delay time. However, such delay circuits are comparatively expensive and may not be commercially available for the specific delay time which is needed in a given application. In such cases, a user specified device would have to be developed which would increase the costs even more.
In another known implementation which is shown in FIGS. 5(A) and (B), all the signals PHI, PHIn, RS and CONV are derived from a common basic clock signal CLK using a timing circuit 18 which is made up of a number of digital counters and may be considered as a state machine. In this case, the durations of the H and L periods of all signals output by the timing circuit 18 can only be integral multiples of the period of the basic clock signal CLK. Accordingly, in order to achieve a sufficient time resolution, the basic clock signal CLK must have a comparatively high frequency. Such a high frequency clock signal may be difficult to generate and may be unfavorable because it leads to the generation of electromagnetic noise and to problems of electromagnetic compatibility (EMC).
In addition, these known techniques have the disadvantage that the digital output signal of the ADC 14 is delayed relative to the clock signal PHI, so that an additional step is necessary for synchronizing the digital output of the ADC 14 with the system clock CLK.
This specific problem is addressed by a system disclosed in DE-A-36 24 252. In this system, as is shown in FIG. 6, the clock signal PHI, PHIn is directly applied to the control input of the ADC 14 and serves as the converter clock signal CONV. The correct time relationship between the operations of the CCD-array 10 and the ADC 14 is established by appropriately delaying the clock signal PHI, PHIn supplied to the clock input of the CCD-array 10. Thus, the output of the ADC 14 remains synchronized with the original clock signal PHI, PHIn. However, the above-mentioned problems relating to the provision of a delay device which can delay a logic clock signal with sufficient accuracy and reliability are still encountered in this system.